-- Rejestr 4-bitowy zatrzaskowy
-- Wejscie danych: DATAIN[3..0]
-- Wyjscie danych: DATAOUT[3..0]
-- Wejscia sterujace:
-- LAE# (latch enable)

library IEEE;
use IEEE.Std_Logic_1164.all;

entity REG4_LATCH is
  generic (delay : time := 5 ns);
  port (LAE     : in std_logic;
        DATAIN  : in std_logic_vector(3 downto 0);
        DATAOUT : out std_logic_vector(3 downto 0));
end entity REG4_LATCH;

architecture REG4_LATCH_arch of REG4_LATCH is
begin
  process(LAE, DATAIN)
    begin
      if (LAE = '0') then
        DATAOUT <= DATAIN after delay;
      end if;
  end process;
end architecture REG4_LATCH_arch;
